Sub-micron integrated circuits (ICs) require that the device surfaces be planarized at their metal inter-connect steps. Chemical mechanical polishing (CMP) is the technology of choice for planarizing semiconductor wafer surfaces. The IC transistor packing density has been doubled about every 18 months for some number of years and there has been consistent effort to maintain this trend.
There are at least two methods by which to increase the packing density of transistors on a chip. The first method is to increase the device or die size. This is not always the best method, however, because as the die size increases, the die yield per wafer may typically decrease. Since the defect density per unit area is the constraint factor, the amount of defect-free dies per area decreases as the die size increases. Not only will the yield be lower, but the number of dies that can be stepped (printed) on the wafer will also decrease. The second method is to shrink the size of the transistor feature. Smaller transistors mean a higher switching speed, which is an added benefit. By decreasing the transistor size, more transistors and more logic functions or memory bits can be packed into the same device area without increasing die size.
Sub-half micron technology has been rapidly evolved into sub-quarter micron technology in the past few years alone. The number of transistors being fabricated on each chip has increased enormously—from hundreds of thousands transistors per chip three years ago to several million transistors per chip today. This density is expected to increase even further in the near future. The current solution to the challenge is to build layers upon layers of inter-connect wiring with insulating (dielectric) thin films in between. The wiring is also connectable vertically through vias; to achieve all electrical paths as required by the integrated circuit functions.
Inlaid metal line structure, using inlaid metal lines embedded in insulating dielectric layers, allows for metal wiring connections to be made on the same plane as well as on an up and down direction through plasma etched trenches and vies in the dielectric layer. Theoretically, these connection planes can be built with as many layers on top of each other as desired, as long as each layer is well planarized with CMP process. The ultimate limit of the interconnect is formed by the connection resistance (R) and the proximity capacitance (C). The so-called RC constant limits the signal-to-noise ratio and causes the power consumption to increase, rendering the chip non-functional. According to industry projections, the number of transistors to be integrated on a chip will be as many as one billion, and the number of layers of interconnect will increase to up to nine layers or more.
To meet the predicted inter-connect requirements, the CMP process and CMP tool performance would advantageously be improved to achieve reduce the wafer edge exclusion due to over- and under-polishing from 6 mm to less than 3 mm so that the physical area from which large dies may be formed, and reduce polishing non-uniformity by providing a polishing head that is able to apply uniform and appropriate force across the entire surface of the wafer during polishing. Current variations in film uniformities after CMP, at the wafer edge (2–15 mm from the edge) result in lost die yield in the outer edges of the wafer. This edge non-uniformity is due to either over or under polishing near the wafer edge. By providing a CMP polishing head with the ability to adjust the amount of edge polishing to compensate for over or under polishing, significant yield improvements can be achieved.
Integrated circuits are conventionally formed on substrates, particularly silicon wafers, by the sequential deposition of one or more layers, which layers may be conductive, insulative, or semiconductive. These structures are sometimes referred to as the multi-layer metal structures (MIM's) and are important relative to achieving close-packing of circuit elements on the chip with the ever decreasing design rules.
Flat panel displays such as those used in notebook computers, personal data assistants (PDAs), cellular telephones, and other electronic devices, may typically deposit one or more layers on a glass or other transparent substrate to form the display elements such as active or passive LCD circuitry. After each layer is deposited, the layer is etched to remove material from selected regions to create circuitry features. As a series of layers are deposited and etched, the outer or topmost surface of the substrate becomes successively less planar because the distance between the outer surface and the underlying substrate is greatest in regions of the substrate where the least etching has occurred, and the distance between the outer surface and the underlying substrate is least in regions where the greatest etching has occurred. Even for a single layer, the non-planar surface takes on an uneven profile of peaks and valleys. With a plurality of patterned layers, the difference in the height between the peaks and valleys becomes much more severe, and may typically vary by several microns.
A non-planar upper surface is problematic respective of surface photolithography used to pattern the surface, and respective of layers that may fracture if deposited on a surface having excessive height variation. Therefore, there is a need to planarize the substrate surface periodically to provide a planar layer surface. Planarization removes the non-planar outer surface to form a relatively flat, smooth surface and involves polishing away the conductive, semiconductive, or insulative material. Following planarization, additional layers may be deposited on the exposed outer surface to form additional structures including interconnect lines between structures, or the upper layer may be etched to form vias to structures beneath the exposed surface. Polishing generally and chemical mechanical polishing (CMP) more particularly are known methods for surface planarization.
The polishing process is designed to achieve a particular surface finish (roughness or smoothness) and a flatness (freedom from large scale topography). Failure to provide minimum finish and flatness may result in defective substrates, which in turn may result in defective integrated circuits.
During CMP, a substrate such as a semiconductor wafer, is typically mounted with the surface to be polished exposed, on a wafer carrier which is part of or attached to a polishing head. The mounted substrate is then placed against a rotating polishing pad disposed on a base portion of the polishing machine. The polishing pad is typically oriented such that it's flat polishing surface is horizontal to provide for even distribution of polishing slurry and interaction with the substrate face in parallel opposition to the pad. Horizontal orientation of the pad surface (the pad surface normal is vertical) is also desirable as it permits the wafer to contact the pad at least partially under the influence of gravity, and at the very least interact in such manner that the gravitational force is not unevenly applied between the wafer and the polishing pad. In addition to the pad rotation, the carrier head may rotate to provide additional motion between the substrate and polishing pad surface. The polishing slurry, typically including an abrasive suspended in a liquid and for CMP at least one chemically-reactive agent, may be applied to the polishing pad to provide an abrasive polishing mixture, and for CMP an abrasive and chemically reactive mixture at the pad substrate interface. Various polishing pads, polishing slurries, and reactive mixtures are known in the art, and which is combination allow particular finish and flatness characteristics to be achieved. Relative speed between the polishing pad and the substrate, total polishing time, and the pressure applied during polishing, in addition to other factors influence the surface flatness and finish, as well as the uniformity. It is also desirable that the polishing of successive substrates, or where a multiple head polisher is used, all substrates polished during any particular polishing operation are polished to the same extent, including removal of substantially the same amount of material and providing the same flatness and finish. CMP and wafer polishing generally are well known in the art and not described in further detail here.
In U.S. Pat. No. 5,205,082 there is described a flexible diaphragm mounting of the sub-carrier having numerous advantages over earlier structures and methods, and U.S. Pat. No. 5,584,751 provides for some control of the down force on the retaining ring through the use of a flexible bladder; however, neither these patents describe structure for direct independent control of the pressure exerted at the interface of the wafer and retaining ring, or any sort of differential pressure to modify the edge polishing or planarization effects.
In view of the foregoing, there is a need for a chemical mechanical polishing apparatus which optimizes polishing throughput, flatness uniformity, and finish, while minimizing the risk of contamination or destruction of any substrate.
In view of the above, there remains a need for a polishing head that provides a substantially uniform pressure across the substrate surface being polished, that maintains the substrate substantially parallel to the polishing pad during the polishing operation, and that maintains the substrate within the carrier portion of the polishing head without inducing undesirable polishing anomalies at the periphery of the substrate.